1. Field
Exemplary embodiments of the present invention relate generally to a data output circuit.
2. Description of the Related Art
FIG. 1 is a circuit diagram illustrating the configuration of a conventional output driver.
Referring to FIG. 1, an output driver may include first and second driving units 110 and 120 coupled to an output pad DQ.
The first driving unit 110 may pull-up drive the output pad DQ with driving power determined by a first control code PCODE<0:5> in response to a data signal DATA. The first driving unit 110 may include a plurality of first and second PMOS transistors P1_0 to P1_5 and P2_0 to P2_5 coupled between the output pad DQ and a pull-up power node 101. A power supply voltage VDD is applied to the pull-up power node. The first PMOS transistors P1_0 to P1_5 may be turned on/off in response to a corresponding first control signal among a plurality of first control signals PCODE<0> to PCODE<5> included in the first control code PCODE<0:5>. The second PMOS transistors P2_0 to P2_5 may be turned on/off in response to the data signal DATA.
The second driving unit 120 may pull-down drive the output pad DQ with driving power determined by a second control code NCODE<0:5> in response to the data signal DATA. The second driving unit 120 may include a plurality of first and second NMOS transistors N1_0 to N1_5 and N2_0 to N2_5 coupled between the output pad DQ and a pull-down power node 102. A base voltage VSS is applied to the pull-down power node 102. The first NMOS transistors N1_0 to N1_5 may be turned on/off in response to a corresponding second control signal among a plurality of second control signals NCODE<0> to NCODE<5> included in the second control code NCODE<0:5>. The second NMOS transistors N2_0 to N2_5 may be turned on/off in response to the data signal DATA.
FIG. 2 is a diagram explaining power-up of a semiconductor device included in the output driver illustrated in FIG. 1.
Referring to FIG. 2, the level of the power supply voltage VDD increases for the power up of the semiconductor device. Briefly, the power up of the semiconductor device may represent an operation of turning on the semiconductor device.
When the level of the power supply voltage VDD is stabilized through a ramp-up section RAMP_UP, during which the level of the power supply voltage VDD increases, a power-up signal PWR_UP can be enabled. The first and second control codes PCODE<0:5> and NCODE<0:5> have arbitrary values from when the power-up signal PWR_UP is enabled to when an initialization signal RST is enabled. For this reason, some transistors among the PMOS transistors P1_0 to P1_5 and first NMOS transistors N1_0 to N1_5 are turned on, so that leakage current may occur between the output pad DQ and the voltage nodes 101 and 102.